Current mirror circuit with minimized input to output current error

ABSTRACT

A current mirror circuit for outputting an output current in proportion to an input current, comprises a first transistor having a collector through which the input current flows, a second transistor having a base connected to a base of the first transistor and a collector through which the output current flows, a third transistor having a base connected to a collector of the first transistor, and an emitter through which a predetermined current flows, and a fourth transistor having a base connected to an emitter of the third transistor, and an emitter connected to the base of the first and second transistors. A variable current source is connected between an emitter of the third transistor and ground to cause the predetermined current to flow through the third transistor. The value of the predetermined current is variable. An input current detecting circuit is provided to detect the input current for controlling the variable current source so as to maintain the predetermined current in proportion to the input current.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a current mirror circuit, and more specifically to a current mirror circuit suitable for a received signal indicator provided in a receiver for detecting a received electric field strength.

2. Description of Related Art

A receiver used in a communication system such as a PHS (personal handy-phone system) generally includes a received signal indicator for detecting a variation of a received electric field strength.

Referring to FIG. 1, there is shown a block diagram illustrating the construction of a conventional received signal indicator.

The shown received signal indicator, designated with Reference Numeral 102, is connected to a multi-stage amplifier 101 composed of a plurality of cascaded amplifiers for amplifying a received signal having an input power Pin. The received signal indicator 102 includes a detection circuit 103 for detecting an output power supplied from each of the amplifiers of the multi-stage amplifier 101, and a current mirror circuit 104 and a resistor R_(L) for outputting, on the basis of an output of the detection circuit 103, a detection voltage V_(S) in proportion to the input power Pin of the detection circuit 101. With this construction, a current Iref in proportion to the input power Pin of the detection circuit 101 is outputted from the detection circuit 103. Since the current mirror circuit 104 acting as a buffer amplifier is connected to the output of the detection circuit 103, an output current I_(O) of the current mirror circuit 104 is caused to flow through the resistor R_(L). Thus, the detection voltage V_(S) in proportion to the input power Pin of the detection circuit 101 is outputted from between opposite ends of the resistor R_(L).

Here, the current mirror circuit is a circuit operating to maintain a predetermined ratio between the input current Iref and the output current I_(O). Referring to FIG. 2, there is shown a circuit diagram of the simplest construction of the current mirror circuit, which is well known to persons skilled in the art.

In the circuit construction shown in FIG. 2, however, since a base current I_(B1) flowing between a base and an emitter of a transistor Q₁₀₁ and a base current I_(B2) flowing between a base and an emitter of a transistor Q₁₀₂ flows into the input current Iref, the output current I_(O) becomes as follows:

    I.sub.O =Iref+I.sub.B1 +I.sub.B2

In order to reduce the influence of the base currents, a current mirror circuit as shown in FIG. 3 has been proposed in the prior art.

The current mirror circuit shown in FIG. 3 includes a transistor Q₁₁₁ having an emitter connected through a resistor R₁₁₁ to a power supply voltage V_(CC), a transistor Q₁₁₂ having a base connected to a base of the transistor Q₁₁₁ and an emitter connected through a resistor R₁₁₂ to the power supply voltage V_(CC), a transistor Q₁₁₃ having a collector connected to the power supply voltage V_(CC) and a base connected to a collector of the transistor Q₁₁₁, a transistor Q₁₁₄ having an emitter connected the bases of the transistors Q₁₁₁ and Q₁₁₂, a base connected to an emitter of the transistor Q₁₁₃, and a collector connected to ground, and a constant current source 112 having one end connected to the emitter of the transistor Q₁₁₃ and the other end connected to the ground.

Here, assume that a collector current of the transistor Q₁₁₁ is I_(C1), a collector current of the transistor Q₁₁₂ is I_(C2) (=I_(O)), a base current of the transistor Q₁₁₃ is I_(B3), an emitter current of the transistor Q₁₁₄ is I_(E4), a base current of the transistor Q₁₁₄ is I_(B4), and a current of the constant current source 112 is Ia. A relation between the output current I_(O) and the input current Iref is expressed as follows: ##EQU1## where h_(FEP) is a current amplification factor of the PNP transistors (Q₁₁₁, Q₁₁₂ and Q₁₁₄) and h_(FEN) is a current amplification factor of the NPN transistors (Q₁₁₃).

As seen from the above equation (1), the prior art current mirror circuit shown in FIG. 3 has an error of Ia/(h_(FEN) +1) between the input current Iref and the output current I_(O). However, since it is generally that h_(FEP), h_(FEN) >>1, the error in the prior art current mirror circuit shown in FIG. 3 can be made smaller than that in the current mirror circuit shown in FIG. 2.

However, in the case that the prior art current mirror circuit shown in FIG. 3 is incorporated in the received signal indicator, since the value of the input current Iref varies in a logarithmic characteristics, the error becomes large when the value of the input current Iref becomes small. The reason for this is that, since the error of Ia/(h_(FEN) +1) exists between the input current Iref and the output current I_(O) as shown in the equation (1), the smaller the value of the input current Iref becomes, the larger the influence of the output current Ia (constant value) of the constant current source becomes non-negligibly. In addition, since the value of the current amplification factors h_(FEP) and h_(FEN) greatly varies dependently upon the manufacturing process, if the value of the current amplification factors h_(FEP) and h_(FEN) becomes small, the error between the input current Iref and the output current I_(O) becomes large.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide a current mirror circuit which has overcome the above mentioned defect of the conventional one.

Another object of the present invention is to provide a current mirror circuit having a minimized error of an output current to an input current even if the change of the input current is large and even if the variation of current amplification factors is large.

The above and other objects of the present invention are achieved in accordance with the present invention by a current mirror circuit for outputting an output current in proportion relation to an input current, comprising:

a first transistor having a collector through which the input current flows;

a second transistor having a base connected to a base of the first transistor and a collector through which the output current flows;

a third transistor having a base connected to a collector of the first transistor, and an emitter through which a predetermined current flows;

a fourth transistor having a base connected to an emitter of the third transistor, and an emitter connected to the base of the first and second transistors;

a variable current source connected to cause the predetermined current to flow through the third transistor, the value of the predetermined current being variable; and

an input current detecting circuit detecting the input current for controlling the variable current source so as to maintain the predetermined current in proportion to the input current.

In a preferred embodiment of the current mirror circuit, the input current detecting circuit includes:

a fifth transistor having a base connected to the bases of the first and second transistors and a collector through which a current equal to the current flowing through the collector of the first transistor flows;

a sixth transistor connected in series to the fifth transistor; and

a seventh transistor having a base connected to a collector of the sixth transistor and a collector connected to a base of the sixth transistor.

In addition, the variable current source includes an eighth transistor having a base connected to the base of the sixth transistor.

According to another aspect of the present invention, there is provided a current mirror circuit for outputting an output current in proportion to an input current, comprising:

a first transistor having a collector through which the input current flows;

a second transistor having a base connected to a base of the first transistor and a collector through which the output current flows;

a third transistor having a base connected to a collector of the first transistor, and an emitter through which a predetermined current flows;

a variable current source connected to cause the predetermined current to flow through the third transistor, the value of the predetermined current being variable; and

an input current detecting circuit detecting the input current for controlling the variable current source so as to maintain the predetermined current in proportion to the input current.

In a preferred embodiment of this current mirror circuit, the input current detecting circuit includes:

a fourth transistor having a base connected to the emitter of the third transistor and an emitter connected to the bases of the first and second transistors; and

a fifth transistor connected in series to the fourth transistor, and having a collector and a base connected to each other.

In addition, the variable current source includes a sixth transistor having a base connected to the base of the fifth transistor.

In a specific embodiment, the above mentioned input current can be a current outputted from a detecting circuit for detecting a received electric field strength.

In the current mirror circuit having the above mentioned construction, the predetermined current is caused to flow through the third transistor by the variable current source, and the value of the predetermined current is variable. In addition, the input current is detected by the input current detecting circuit, and the current flowing through the variable current source is controlled to be in proportion to the input current by the input current detecting circuit. Therefore, if the input current becomes small, the current of the variable current source correspondingly becomes small. Accordingly, even if the input current greatly changes, the error between the input current and the output current in the current mirror circuit can be minimized.

The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating the construction of a conventional received signal indicator;

FIG. 2 is a circuit diagram of the simplest construction of the current mirror circuit, which is well known to persons skilled in the art;

FIG. 3 is a circuit diagram of another prior art current mirror circuit;

FIG. 4 is a block diagram illustrating a basic construction of the current mirror circuit in accordance with the present invention;

FIG. 5 is a circuit diagram of a first embodiment of the current mirror circuit in accordance with the present invention;

FIG. 6 is a graph illustrating a relation between the output current and the change of the input current in the current mirror circuit shown in FIG. 5;

FIG. 7 is a graph illustrating a relation between the output current to input current ratio and the variation of the current amplification factors in the current mirror circuit shown in FIG. 5;

FIG. 8 is a circuit diagram of a second embodiment of the current mirror circuit in accordance with the present invention;

FIG. 9 is a graph illustrating a relation between the output current and the change of the input current in the current mirror circuit shown in FIG. 8;

FIG. 10 is a graph illustrating a relation between the output current to input current ratio and the variation of the current amplification factors in the current mirror circuit shown in FIG. 8;

FIG. 11 is a circuit diagram of a third embodiment of the current mirror circuit in accordance with the present invention; and

FIG. 12 is a circuit diagram of a fourth embodiment of the current mirror circuit in accordance with the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 4, there is shown a block diagram illustrating a basic construction of the current mirror circuit in accordance with the present invention.

The current mirror circuit shown in FIG. 1 includes a transistor Q₁ having an emitter connected through a resistor R₁ to a power supply voltage V_(CC), a transistor Q₂ having a base connected to a base of the transistor Q₁ and an emitter connected through a resistor R₂ to the power supply voltage V_(CC), a transistor Q₃ having a collector connected to the power supply voltage V_(CC), a base connected to a collector of the transistor Q₁, and a transistor Q₄ having an emitter connected to the bases of the transistors Q₁ and Q₂, a base connected to an emitter of the transistor Q₃, and a collector connected to ground. An input current Iref is caused to flow from a collector of the transistor Q₁, and an output current I_(O) is taken from a collector of the transistor Q₂.

The current mirror circuit shown in FIG. 1 also includes a variable current source 2 having one end connected to an emitter of the transistor Q₃ and the other end connected to the ground, and an input current detecting circuit 1 detecting the input current Iref of the current mirror circuit for controlling the output current Ia of the variable current source 2.

With this arrangement, the input current detecting circuit 1 detects the value of the input current Iref for controlling the variable current source 2 so as to maintain the value of the output current Ia of the variable current source 2 in proportion to the value of the input current Iref.

Accordingly, if the input current Iref becomes small, the output current Ia of the variable current source 2 correspondingly becomes small. Thus, even if the input current Iref greatly changes, an error between the input current Iref and the output current I_(O) of the current mirror circuit can be minimized.

As seen from the above, the current mirror circuit in accordance with the present invention shown in FIG. 4 is characterized in that, the constant current source in the prior art current mirror circuit shown in FIG. 3 is replaced with the variable current source 2 having the output current Ia which is changed or varied in accordance with the change of the input current Iref by the input current detecting circuit 1.

Referring to FIG. 5, there is shown a circuit diagram of a first embodiment of the current mirror circuit in accordance with the present invention. In FIG. 5, elements corresponding to those shown in FIG. 4 are given the same Reference Numerals, and explanation will be omitted.

In the current mirror circuit shown in FIG. 5, an input current detecting circuit 11 (corresponding to the input current detecting circuit 1 in FIG. 1) includes a transistor Q₅ having a base connected to the bases of the transistors Q₁ and Q₂ and an emitter connected through a resistor R₃ to the power supply voltage V_(CC), a transistor Q₆ having a collector connected to the power supply voltage V_(CC) and a base connected to a collector of the transistor Q₅, and a transistor Q₈ having a collector connected to the collector of the transistor Q₅ and the base of the transistor Q₆, a base connected to an emitter of the transistor Q₆, and an emitter connected through a resistor R₅ to the ground. In this input current detecting circuit 11, the transistor Q₅ is connected in the same circuit connection as that of the transistor Q₁, so that a current flowing through the collector of the transistor Q₅ is made equal to the input current Iref, with the result that the input current Iref is equivalently detected.

A variable current source 12 (corresponding to the variable current source 2 in FIG. 1) includes a transistor Q₇ having a collector connected to the emitter of the transistor Q₃, an emitter connected through a resistor R₄ to the ground and a base connected to the emitter of the transistor Q₆ and the base of the transistor Q₈ in the input current detecting circuit 11. Here, if an emitter area ratio between the transistors Q₇ and Q₈ is expressed by Q₇ :Q₈ =N₁ :N₂, respective resistance of the resistors R₄ and R₅ are in the relation of R₄ ·N₁ =R₅ ·N₂.

In the construction shown in FIG. 5, assume that a collector current of the transistor Q₁ is I_(C1), a collector current of the transistor Q₂ is I_(C2) (=I_(O)), a base current of the transistor Q₃ is I_(B3), an emitter current of the transistor Q₄ is I_(E4), a base current of the transistor Q₄ is I_(B4), a collector current of the transistor Q₅ is I_(C5), a base current of the transistor Q₆ is I_(B6), an emitter current of the transistor Q₆ is I_(E6), a collector current of the transistor Q₈ is I_(C8), and a collector current of the transistor Q₇ is I_(C7) (=Ia). In this condition, a relation between the output current I_(O) and the input current Iref is expressed as follows: ##EQU2## where h_(FEP) is a current amplification factor of the PNP transistors (Q₁, Q₂, Q₄ and Q₅) and h_(FEN) is a current amplification factor of the NPN transistors (Q₃, Q₆, Q₇ and Q₈).

Thus, if the input current Iref changes, the collector current I_(C8) of the transistor Q₈ changes with the intermediary of the transistor Q₅, and the collector current I_(C7) of the transistor Q₇ changes in proportion to the collector current I_(C8).

In addition, as seen from the equation (2), since the output current I_(O) is a function of the input current Iref, if the input current Iref becomes a small value, the current I_(C7) (=Ia) flowing through the variable current source 12 also becomes small, and therefore, the base current I_(B3) of the transistor Q₃ correspondingly becomes small, with the result that the error between the input current Iref and the output current I_(O) becomes small. Since the error is in proportion to 1/(h_(FEN) +1)², even if the value of the current amplification factors h_(FEN) and h_(FEP) becomes small, the error between the input current Iref and the output current I_(O) becomes small in comparison with the prior art current mirror circuit.

Here, a relation between the input current Iref and the output current I_(O) in the current mirror circuit shown in FIG. 5 becomes as shown in the graph of FIG. 6 (where a mirror ratio=1). For reference, the graph of FIG. 6 additionally shows the relation between the input current Iref and the output current I_(O) in the prior art current mirror circuit. In addition, a relation between the output current to input current ratio "I_(O) /Iref" and the variation of the current amplification factors h_(FEN) and h_(FEP) in the current mirror circuit shown in FIG. 5 becomes as shown in the graph of FIG. 7 (where a mirror ratio=1). For reference, the graph of FIG. 7 additionally shows the relation between the output current to input current ratio "I_(O) /Iref" and the variation of the current amplification factors h_(FEN) and h_(FEP) in the prior art current mirror circuit.

It would be understood from FIG. 6 that, in the current mirror circuit of the first embodiment, even if the value of the input current Iref greatly changes in a range of a few digits, the value of the output current I_(O) closely follows the value of the input current Iref, and even if the input current Iref becomes small, the error never becomes large, clearly differently from the prior art. In addition, it would be understood from FIG. 7 that, in the current mirror circuit of the first embodiment, the error is maintained at a small value independently of the variation of the current amplification factors h_(FEN) and h_(FEP).

Referring to FIG. 8, there is shown a circuit diagram of a second embodiment of the current mirror circuit in accordance with the present invention. In FIG. 8, elements corresponding to those shown in FIG. 4 are given the same Reference Numerals, and explanation will be omitted.

In the current mirror circuit shown in FIG. 8, an input current detecting circuit 21 (corresponding to the input current detecting circuit 1 in FIG. 1) includes a transistor Q₁₅ having an emitter connected to the bases of the transistors Q₁ and Q₂ and a base connected to the emitter of the transistor Q₃, and a transistor Q₁₈ having a collector and a base connected in common to a collector of the transistor Q₁₅ and an emitter connected through a resistor R₁₅ to the ground. In this input current detecting circuit 21, the transistor Q₁₅ detects the base current of the transistor Q₃ to feed back the detection result to the bases of the transistors Q₁ and Q₂, similarly to the transistor Q₄ in FIG. 4. In addition, the transistors Q₁₅ and Q₁₈ detect the base currents of the transistors Q₁ and Q₂, so that the input current Iref of the current mirror circuit is equivalently detected.

A variable current source 22 (corresponding to the variable current source 2 in FIG. 1) includes a transistor Q₁₇ having a collector connected to the emitter of the transistor Q₃, an emitter connected through a resistor R₁₄ to the ground and a base connected to the base of the transistor Q₁₈ in the input current detecting circuit 21. Here, if an emitter area ratio between the transistors Q₁₇ and Q₁₈ is expressed by Q₁₇ :Q₁₈ =N₁ :N₂, respective resistance of the resistors R₁₄ and R₁₅ are in the relation of R₁₄ ·N₁ =R₁₅ ·N₂.

In the construction shown in FIG. 8, assume that a collector current of the transistor Q₁ is I_(C1), a collector current of the transistor Q₂ is I_(C2) (=I_(O)), a base current of the transistor Q₁ is I_(B1), a base current of the transistor Q₂ is I_(B2), a base current of the transistor Q₃ is I_(B3), a base current of the transistor Q₁₅ is I_(B15), and a collector current of the transistor Q₁₇ is I_(C17) (=Ia). In this condition, a relation between the output current I_(O) and the input current Iref is expressed as follows: ##EQU3## where h_(FEP) is a current amplification factor of the PNP transistors (Q₁, Q₂, and Q₁₅) and h_(FEN) is a current amplification factor of the NPN transistors (Q₃, Q₁₇ and Q₁₈).

In the circuit shown in FIG. 8, since a current mirror circuit is constituted of the transistor Q₁₇ and the transistor Q₁₈ in the input current detecting circuit 21, if the input current Iref changes, the collector current I_(C18) of the transistor Q₁₈ changes, and the collector current I_(C17) of the transistor Q₁₇ changes in proportion to the collector current I_(C18).

In addition, as seen from the equation (3), since the output current I_(O) is a function of the input current Iref, if the input current Iref becomes a small value, similarly to the first embodiment, the current I_(C17) (=Ia) flowing through the variable current source 22 also becomes small, and therefore, the base current I_(B3) of the transistor Q₃ correspondingly becomes small, with the result that the error between the input current Iref and the output current I_(O) becomes small.

Here, a relation between the input current Iref and the output current I_(O) in the current mirror circuit shown in FIG. 8 becomes as shown in the graph of FIG. 9 (where a mirror ratio=1). In addition, a relation between the output current to input current ratio "I_(O) /Iref" and the variation of the current amplification factors h_(FEN) and h_(FEP) in the current mirror circuit shown in FIG. 8 becomes as shown in the graph of FIG. 10 (where a mirror ratio=1).

It would be understood from FIG. 9 that, in the current mirror circuit of the second embodiment, similarly to the first embodiment, even if the value of the input current Iref greatly changes in a range of a few digits, the value of the output current I_(O) closely follows the value of the input current Iref, and even if the input current Iref becomes small, the error never becomes large, clearly differently from the prior art. In addition, it would be understood from FIG. 10 that, in the current mirror circuit of the second embodiment, the error is maintained at a small value independently of the variation of the current amplification factors h_(FEN) and h_(FEP). On the other hand, since the second embodiment can be constituted of the transistors of the number smaller than that of the transistors required in the first embodiment, the necessary circuit area can be reduced.

Referring to FIG. 11, there is shown a circuit diagram of a third embodiment of the current mirror circuit in accordance with the present invention. In FIG. 11, elements corresponding to those shown in FIG. 4 are given the same Reference Numerals, and explanation will be omitted.

In the current mirror circuit shown in FIG. 11, an input current detecting circuit 31 (corresponding to the input current detecting circuit 1 in FIG. 1) includes a transistor Q₂₅ having a base connected to the bases of the transistors Q₁ and Q₂ and an emitter connected through a resistor R₂₃ to the power supply voltage V_(CC), and a transistor Q₂₈ having a collector and a base connected in common to the collector of the transistor Q₂₅ and the collector of the transistor Q₄, and an emitter connected through a resistor R₂₅ to the ground. In this input current detecting circuit 31, the transistor Q₂₅ is connected in the same circuit connection as that of the transistor Q₁, so that a current flowing through the collector of the transistor Q₂₅ is made equal to the input current Iref, with the result that the input current Iref is equivalently detected.

A variable current source 32 (corresponding to the variable current source 2 in FIG. 1) includes a transistor Q₂₇ having a collector connected to the emitter of the transistor Q₃, an emitter connected through a resistor R₂₄ to the ground and a base connected to the base of the transistor Q₂₈ in the input current detecting circuit 31.

Referring to FIG. 12, there is shown a circuit diagram of a fourth embodiment of the current mirror circuit in accordance with the present invention. In FIG. 12, elements corresponding to those shown in FIG. 4 are given the same Reference Numerals, and explanation will be omitted.

In the current mirror circuit shown in FIG. 12, an input current detecting circuit 41 (corresponding to the input current detecting circuit 1 in FIG. 1) includes a transistor Q₃₅ having a base connected to the bases of the transistors Q₁ and Q₂ and an emitter connected through a resistor R₃₃ to the power supply voltage V_(CC), and a transistor Q₃₈ having a collector connected to the collector of the transistor Q₃₅, a base connected to the collector of the transistor Q₄, and an emitter connected through a resistor R₃₅ to the ground. In this input current detecting circuit 41, the transistor Q₃₅ is connected in the same circuit connection as that of the transistor Q₁, so that a current flowing through the collector of the transistor Q₃₅ is made equal to the input current Iref, with the result that the input current Iref is equivalently detected.

A variable current source 42 (corresponding to the variable current source 2 in FIG. 1) includes a transistor Q₃₇ having a collector connected to the emitter of the transistor Q₃, an emitter connected through a resistor R₃₄ to the ground and a base connected to the base of the transistor Q₃₈ in the input current detecting circuit 41.

In these third and fourth embodiments, similarly to the first and second embodiments, if the input current Iref becomes small, the current flowing through the variable current source correspondingly becomes small, and therefore, the base current of the transistor Q₃ becomes small, with the result that the error between the input current Iref and the output current I_(O) becomes small. In addition, since the third and fourth embodiments can be constituted of the transistors of the number smaller than that of the transistors required in the first embodiment, the necessary circuit area can be reduced.

As mentioned above, the current mirror circuit in accordance with the present invention is advantageous in that even if the value of the input current Iref greatly changes in a range of a few digits, and even if the input current Iref becomes extremely small, the error between the input current and the output current can be maintained at a minimized level. In addition, the error is maintained at the minimized value independently of the variation of the current amplification factors h_(FEN) and h_(FEP).

The invention has thus been shown and described with reference to the specific embodiments. However, it should be noted that the present invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claims. 

I claim:
 1. A current mirror circuit for outputting an output current in proportion to an input current, comprising:a first transistor having a collector through which said input current flows; a second transistor having a base connected to a base of said first transistor and a collector through which said output current flows; a third transistor having a base connected to a collector of said first transistor, and an emitter through which a predetermined current flows; a fourth transistor having a base connected to an emitter of said third transistor, and an emitter connected to said base of said first and second transistors; a variable current source connected to cause said predetermined current to flow through said third transistor, the value of said predetermined current being variable; and an input current detecting circuit detecting said input current for controlling said variable current source so as to maintain said predetermined current in proportion to said input current.
 2. A current mirror circuit claimed in claim 1 wherein said input current detecting circuit includes:a fifth transistor having a base connected to said bases of said first and second transistors and a collector through which a current equal to the current flowing through said collector of said first transistor flows; a sixth transistor connected in series to said fifth transistor; and a seventh transistor having a base connected to an emitter of said sixth transistor and a collector connected to a base of said fourth transistor.
 3. A current mirror circuit claimed in claim 2 wherein said variable current source includes an eighth transistor having a base connected to said base of said sixth transistor.
 4. A current mirror circuit claimed in claim 3 wherein said input current is a current outputted from a detecting circuit for detecting a received electric field strength.
 5. A current mirror circuit claimed in claim 2 wherein said input current is a current outputted from a detecting circuit for detecting a received electric field strength.
 6. A current mirror circuit claimed in claim 1 wherein said input current detecting circuit includes:a fifth transistor having a base connected to said bases of said first and second transistors and a collector through which a current equal to the current flowing through said collector of said first transistor flows; a sixth transistor having a base and a collector connected in common to said collector of said fifth transistor and said collector of said fourth transistor.
 7. A current mirror circuit claimed in claim 6 wherein said variable current source includes a seventh transistor having a base connected to said base of said sixth transistor.
 8. A current mirror circuit claimed in claim 7 wherein said input current is a current outputted from a detecting circuit for detecting a received electric field strength.
 9. A current mirror circuit claimed in claim 6 wherein said input current is a current outputted from a detecting circuit for detecting a received electric field strength.
 10. A current mirror circuit claimed in claim 1 wherein said input current detecting circuit includes:a fifth transistor having a base connected to said bases of said first and second transistors and a collector through which a current equal to the current flowing through said collector of said first transistor flows; a sixth transistor having a collector connected to said collector of said fifth transistor, and a base connected to said collector of said fourth transistor.
 11. A current mirror circuit claimed in claim 10 wherein said variable current source includes a seventh transistor having a base connected to said base of said sixth transistor.
 12. A current mirror circuit claimed in claim 11 wherein said input current is a current outputted from a detecting circuit for detecting a received electric field strength.
 13. A current mirror circuit claimed in claim 10 wherein said input current is a current outputted from a detecting circuit for detecting a received electric field strength.
 14. A current mirror circuit for outputting an output current in proportion to an input current, comprising:a first transistor having a collector through which said input current flows; a second transistor having a base connected to a base of said first transistor and a collector through which said output current flows; a third transistor having a base connected to a collector of said first transistor, and an emitter through which a predetermined current flows; a variable current source connected to cause said predetermined current to flow through said third transistor, the value of said predetermined current being variable; and an input current detecting circuit detecting said input current for controlling said variable current source so as to maintain said predetermined current in proportion to said input current.
 15. A current mirror circuit claimed in claim 14 wherein said input current detecting circuit includes:a fourth transistor having a base connected to said emitter of said third transistor and an emitter connected to said bases of said first and second transistors; and a fifth transistor connected in series to said fourth transistor, and having a collector and a base connected to each other.
 16. A current mirror circuit claimed in claim 15 wherein said variable current source includes a sixth transistor having a base connected to said base of said fifth transistor.
 17. A current mirror circuit claimed in claim 16 wherein said input current is a current outputted from a detecting circuit for detecting a received electric field strength.
 18. A current mirror circuit claimed in claim 15 wherein said input current is a current outputted from a detecting circuit for detecting a received electric field strength. 